Modern integrated circuits have become ever more complex. Memory chips, especially, have become ever denser and ever smaller as the art has progressed. The complexity of modern electronic devices means that, though unit cost is small, implementing a design on silicon can be enormously expensive. In order to perform the tasks in a cost effective manner, both pre-layout and post-layout simulation is vital to the evaluation of a design.
Pre-layout simulation of any design is only as effective as the information fed to the simulation engine. Once, digital designs were large enough that digital considerations were dominant over any analog considerations and were easily learned and input to a simulation netlist. Now, as integrated circuits move to incorporate ever smaller features, these high-speed, low-power, digital circuits exhibit increasingly analog behavior because of complex electrical and physical interactions in and among the physical features of the silicon. These include inductance effects, capacitance effects, resistance, cross coupling, and electron migration; phenomena that may not be understood in pre-layout but must be known and input into a netlist in post-layout simulation and must be known in order to characterize the device. This is vital to avoid a non-functional design when fabricated that was successfully verified in pre-layout simulation.
Furthermore, the integration of modern, high-density, chip designs into the multi-device systems in which they ultimately function must account for device characteristics as actually implemented. Characteristics can deviate from design expectations due to the complex internal interaction phenomena mentioned above. Determining these phenomena must be accomplished through post-layout verification because performance cannot be simply extrapolated from the isolated analysis of idealized performance of individual cells or elements. Verification methods based on full-chip circuit-level simulation are meeting increasing requirements for the larger capacity, faster, and more accurate verification and analysis needed to deliver first-time working silicon devices, and first-time working systems.
To achieve reliable simulation and verification characteristics, particularly parasitic resistance and capacitance characteristics, simulation netlists should be back-annotated with data as soon as they are learned and updated. In a memory chip with billions of almost-identical individual features that each have their own characteristics, analyzing each cell or other feature individually presents a task that is time-consuming beyond reach in the modern competitive environment.